Inputs to a NAND gate are A and B are made as below. Output of the NAND gate is

Question

Inputs to a NAND gate are A and B are made as below.

Output of the NAND gate is

(A) a (B) b (C) c (D) d

Tardigrade Admin · Accepted Answer

For an NAND gate, truth table is <img class="img-fluid question-image" alt="image" src="https://cdn.tardigrade.in/img/question/physics/178520f517929df69104649d617034e1-.png" /> Input Out put A B Y 0 0 1 0 1 1 1 0 1 1 1 0 So, no output occurs when both inputs are at higher potentials (1). Till time t4, output (1) occurs because both inputs do not become (1) together.

Input		Out put
$A$	$B$	$Y$
0	0	1
0	1	1
1	0	1
1	1	0

Q. Inputs to a NAND gate are $A$ and $B$ are made as below.

Output of the NAND gate is

a

b

c

d

For an NAND gate, truth table is

Input Out put

$A$ $B$ $Y$

0 0 1

0 1 1

1 0 1

1 1 0

So, no output occurs when both inputs are at higher potentials (1). Till time $t_{4}$ , output (1) occurs because both inputs do not become (1) together.

Q. Inputs to a NAND gate are A and B are made as below. Output of the NAND gate is

a

b

c

d

For an NAND gate, truth table is Input Out put A B Y 0 0 1 0 1 1 1 0 1 1 1 0 So, no output occurs when both inputs are at higher potentials (1). Till time t4​, output (1) occurs because both inputs do not become (1) together.

Q. Inputs to a NAND gate are $A$ and $B$ are made as below.

Output of the NAND gate is

For an NAND gate, truth table is

Input Out put

$A$ $B$ $Y$

0 0 1

0 1 1

1 0 1

1 1 0

So, no output occurs when both inputs are at higher potentials (1). Till time $t_{4}$ , output (1) occurs because both inputs do not become (1) together.