Q.
Inputs to a NAND gate are $A$ and $B$ are made as below.
Output of the NAND gate is

Semiconductor Electronics: Materials Devices and Simple Circuits
Solution:
For an NAND gate, truth table is
Input
Out put
$A$
$B$
$Y$
0
0
1
0
1
1
1
0
1
1
1
0
So, no output occurs when both inputs are at higher potentials (1). Till time $t_{4}$, output (1) occurs because both inputs do not become (1) together.
Input | Out put | ||
---|---|---|---|
$A$ | $B$ | $Y$ | |
0 | 0 | 1 | |
0 | 1 | 1 | |
1 | 0 | 1 | |
1 | 1 | 0 |