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Physics
The logic gate realised from the circuit as shown in figure is (P and Q are inputs and Z is output )
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Q. The logic gate realised from the circuit as shown in figure is $(P$ and $Q$ are inputs and $Z$ is output $)$
A
AND Gate
32%
B
OR Gate
32%
C
NAND Gate
32%
D
NOR Gate
5%
Solution:
$Y=\overline{P \cdot Q}$