Q.
Logic gates $X$ and $Y$ have the truth tables shown below
P
Q
R
P
R
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
1
| P | Q | R | P | R |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | ||
| 1 | 1 | 1 |
Semiconductor Electronics: Materials Devices and Simple Circuits
Solution:
The truth table of the resulting logic circuit by connecting $X$ to $Y$ is as follows:
P
Q
R
R
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1
0
Hence, from the truth table, the combination is equivalent to a single NAND gate.
(OR $X$ is an AND gate and $Y$ is a NOT gate, thus the combination is NOT AND gate, i.e., a NAND gate.)
| P | Q | R | R |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |