A circuit is arranged as shown in figure. The output voltage V 0 is equal to ldots ldots . V

Question

A circuit is arranged as shown in figure. The output voltage V 0 is equal to ldots ldots . V <img class="img-fluid question-image" alt="image" src="https://cdn.tardigrade.in/img/question/physics/2b407718a5c695bb94e8635b61610a4c-.png" /> (A)  (B)  (C)  (D)

Tardigrade Admin · Accepted Answer

As diodes D1 and D2 are in forward bias, so they acted as neligible resistances ⇒ Input voltage become zero <img class="img-fluid question-image" alt="image" src="https://cdn.tardigrade.in/img/question/physics/27b36c87d3323dbf77d5e62c31a12c50-.png" /> ⇒ Input current is zero ⇒ Output current is zero ⇒ V 0=5 volt

Q. A circuit is arranged as shown in figure. The output voltage $V_{0}$ is equal to $\dots\dots . V$

As diodes $D_{1}$ and $D_{2}$ are in forward bias, so they acted as neligible resistances
$\Rightarrow$ Input voltage become zero

$\Rightarrow$ Input current is zero
$\Rightarrow$ Output current is zero
$\Rightarrow V_{0} = 5$ volt

Q. A circuit is arranged as shown in figure. The output voltage V0​ is equal to …….V

As diodes D1​ and D2​ are in forward bias, so they acted as neligible resistances ⇒ Input voltage become zero ⇒ Input current is zero ⇒ Output current is zero ⇒V0​=5 volt

Q. A circuit is arranged as shown in figure. The output voltage $V_{0}$ is equal to $\dots\dots . V$

As diodes $D_{1}$ and $D_{2}$ are in forward bias, so they acted as neligible resistances
$\Rightarrow$ Input voltage become zero

$\Rightarrow$ Input current is zero
$\Rightarrow$ Output current is zero
$\Rightarrow V_{0} = 5$ volt